1. Field of the Invention
The present invention relates to a diamond semiconductor device suitable for field effect transistors, light-emitting diodes, and various sensors and also relates to a method for manufacturing such a device.
2. Description of the Related Art
Diamond has superior properties such as high heat conductivity, wide bandgap, high saturated electron velocity, and high saturated hole velocity. Therefore, diamond is expected to be suitable for high-power devices, high-frequency devices, and semiconductor devices working under severe conditions such as high-temperature conditions or radiation exposure conditions because those devices must have such superior properties.
Examples of a known field effect transistor (FET) including a diamond thin-film include a metal insulator semiconductor field effect transistor (MISFET) including a gate electrode, a channel layer acting as a functional layer, and an insulating layer placed therebetween (see, for example, Japanese Unexamined Patent Application Publication No. 1-158774). A MISFET disclosed in Japanese Unexamined Patent Application Publication No. 1-158774 includes an insulating single crystal diamond substrate, a semiconducting diamond layer disposed on the substrate, and an insulating layer locally placed on the semiconductive diamond layer. The MISFET further includes a source metal electrode, a drain metal electrode, and a gate metal electrode placed on the insulating layer, the source and drain metal electrodes being arranged on the semiconducting diamond layer, the insulating layer being placed between the source and drain metal electrodes. On the other hand, Japanese Patent No. 3273985 discloses a FET having a structure in which a high-resistance diamond layer is placed between an insulating single crystal diamond substrate and a semiconducting diamond layer, the structure being hereinafter referred to as a pip structure.
Examples of methods for manufacturing such transistors include a procedure in which a diamond region is separated into a source and a drain region by an etching process; a diamond section for forming a channel region is exposed; and an insulating layer, a gate electrode, and the like are formed on the diamond section, as described in Japanese Unexamined Patent Application Publication No. 2000-114523. Japanese Unexamined Patent Application Publication No. 2002-57167 discloses a procedure in which a diamond region is separated into a source and a drain region by an etching process, an epitaxial growth process, a selective ion injection process, or another process and a channel region is then formed by epitaxially growing a diamond thin-film so as to cover gaps and areas therearound. Furthermore, Japanese Unexamined Patent Application Publication No. 2002-76369 discloses a procedure in which a diamond region is separated into a source and a drain region by an etching process and a channel region is then formed by epitaxially growing a diamond thin-film on an etched portion.
Examples of a process for etching a diamond piece includes a plasma etching process or another etching process in which a mask is formed on the diamond piece, which is then exposed to plasma formed from gas containing oxygen atoms (see, for example, U.S. Pat. No. 5,344,526 and Japanese Unexamined Patent Application Publication No. 2002-75960).
The known procedures and processes described above have the problems below. In the procedures disclosed in Japanese Unexamined Patent Application Publication Nos. 2000-114523 and 2002-57167, since etching is performed perpendicularly to the diamond surface, the source regions and drain regions formed by etching have end faces substantially perpendicular to the surfaces of devices. There is a problem in that dielectric breakdown occurs at the insulating layers and the channel regions because electric fields between the source and drain regions insulated from the gate regions with the insulating layers are concentrated on corners of these regions when the end faces of the source and drain regions are perpendicular to the device surfaces.
Furthermore, there is a problem in that discontinuities in the insulating layers cause short circuits and discontinuities in the gate electrodes cause a deterioration in performance. For a transistor described in Japanese Unexamined Patent Application Publication No. 2000-114523, when an insulating layer is formed on a gap area by a vapor deposition process or a sputtering process, the insulating layer is grown on a face facing a deposition source or a sputtering target and hardly grown on faces parallel to the deposition source or the sputtering target, that is, end faces of the source region and the drain region; hence, portions of the insulating layer on the end faces thereof have a small thickness. If a substrate for forming the substrate is placed in such a manner that the substrate is slightly inclined, some of the end faces of the source and drain regions are hidden from the deposition source or the sputtering target; hence, the insulating layer is hardly grown on the end faces thereof. In particular, boundary areas between the bottom of an etched area and the end faces of the source and drain regions are hidden from the deposition source or the sputtering target because the end faces are perpendicular to the bottom; hence, the insulating layer is hardly grown on the boundary areas. Such failure in forming the insulating layer causes insulation failure and short circuits, thereby causing a decrease in device reliability and a reduction in yield.
The above problems are supposed to be solved by inclining the end faces of the source and drain regions; however, it is substantially impossible to process the end faces by any existing process with high reproducibility such that the end faces have a controlled shape. At the present moment, a slope with a length of 1 μm or less can hardly be formed on a diamond piece with high hardness by any mechanical polishing process. If possible in future, such a process is not suitable for manufacturing semiconductor devices because mechanical polishing may cause serious internal defects.
When grooves or holes are formed by an etching process, the walls of the grooves or the holes are substantially perpendicular to the bottoms of the grooves or the holes as described above or the boundaries between the walls and bottoms of the grooves or the boundaries between the walls and bottoms of the holes have a semicircular shape, that is, a round shape in cross section in general. In the latter case, there is no problem caused by forming an insulating layer on the bottom of a recession formed by the etching process; however, the thickness of the insulating layer is not uniform because the walls are perpendicular to the bottoms. Since the walls make a sharp angle that is substantially equal to a right angle with the surface of the insulating layer, electric fields are concentrated on the boundaries between the walls and the surface thereof, whereby dielectric breakdown or the like is caused.
In some methods for manufacturing silicon semiconductor devices, an anisotropic etching process in which the etching rate varies depending on the crystal plane is used. In this process, for example, the rate of etching a {111} surface is allowed to be smaller than the rate of etching a {100} surface by the use of a suitable etchant under wet conditions. Therefore, if a mask including a silicon dioxide layer is formed on an area of a {100} surface that must be prevented from being etched and uncovered areas thereof are then exposed to an etchant, slopes having a {111} surface are formed at end portions of the uncovered areas, whereby recessed portions having an inverse trapezoidal shape in cross section parallel to the thickness direction can be formed.
Since diamond has extremely higher chemical resistance as compared with silicon, there is no etchant for etching diamond. Therefore, a plasma etching process is under study. It is supposed that perpendicular etching or anisotropic etching that depends on the crystal orientation can be performed by selecting appropriate conditions using plasma containing oxygen. However, inclined side faces can hardly be formed if perpendicular etching is performed.
For anisotropic etching that depends on the crystal orientation, flat etched faces can hardly be formed because etched faces have irregularities and/or steps due to etch pits that are formed when a material to be etched has internal defects such as dislocations. In the case that the rate of etching the {111} surface is smaller than the rate of etching the {100} surface as described above, if the {100} surface has only a small {111} surface portion, this portion is etched into a pyramid because the rate of etching the portion is low. Furthermore, if the {100} surface is slightly inclined when an etching operation is started, a flat etched face can hardly formed because the {111} surface appears in an early stage of the operation. This phenomenon also occurs when the plasma etching process is used.
When a portion having a desired shape is formed by the plasma etching process, defects due to the impact of ions and the adsorption of impurities are unavoidably formed in inner portions and surfaces of etched areas exposed to plasma. Such defects cause a reduction in charge mobility and an increase in charge mobility and are therefore undesirable.
It is substantially impossible to enhance the performance of semiconductor components such as transistors by forming slopes at end portions of source and drain regions by an etching process because of the problems described above.